1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and particularly to a system LSI equipped with a memory. More particularly, the present invention relates to a configuration of a test interface circuit for externally and directly testing a memory in the system LSI.
2. Description of the Background Art
A system LSI such as a logic merged DRAM has been developed in which a logic such as a processor and an ASIC (Application Specific Integrated Circuit) and a dynamic random access memory (DRAM) of mass storage capacity are integrated on one semiconductor chip (semiconductor substrate). In such a system LSI, interconnection of a logic and a memory such as a DRAM by a multi-bit internal data bus of 128 to 512 bits can attain a data transfer rate higher than that of a general purpose DRAM by at least one or two orders of magnitude.
Since the DRAM and the logic are connected by an internal interconnection, the length of the internal interconnection is sufficiently shorter and has smaller parasitic impedance than an on-board interconnection. That results in achievement of substantial reduction in the charging/discharging current of a data bus as well as signal transmission at high speed. In addition, the number of external pin terminals in the logic can be reduced as compared with a type in which a general purpose DRAM is externally provided for the logic.
From these reasons, the system LSI such as a logic merged DRAM greatly contributes to attaining higher performance of information devices which carry out processing dealing with mass data such as three dimensional graphics processing and image/audio processing.
In the above described system LSI such as a logic merged DRAM, only the logic is coupled to the external pin terminals via a pad. Therefore, when the function of a memory such as a contained DRAM is to be tested, the test needs to be performed through the logic. In this case, however, the logic performs a control operation for testing, which increases the load of the logic. In addition, it becomes necessary to externally supply the logic with an instruction to perform a functional test for a memory such as a DRAM, to give from the logic to the memory a control signal for performing the functional test, and to read out the test result through the logic.
Therefore, the memory functional test in the system LSI such as a logic mixed DRAM is carried out through the logic, and the operating timing margin for the memory and the like cannot be tested correctly.
In view of program capacity as well, the number of test patterns provided by the logic is limited, and sufficient testing cannot be performed. Because of the factors, it is difficult to sufficiently ensure the reliability of a memory such as a DRAM. Since the probability of defect generation in the logic itself becomes higher with increase in the gate scale, the reliability of memory testing is lowered. Therefore, it becomes necessary to directly test a memory such as a DRAM from outside by using a dedicated tester including a memory tester. Hereinafter, the system LSI with contained DRAM is referred to as a DRAM contained system LSI.
FIG. 26 schematically shows a configuration of a conventional DRAM contained system LSI 900.
Referring to FIG. 26, system LSI 900 includes a large scale logic LG coupled to external pin terminals LPGA and performing directed processing, an analog core ACR coupled between large scale logic LG and external pin terminals APG and performing processing for an analog signal, a DRAM core MCR coupled to large scale logic LG through an internal interconnection and storing data required by large scale logic LG, and a test interface circuit TIC disconnecting large scale logic LG and DRAM core MCR in a test mode and coupling an external memory tester to DRAM core MCR through test pin terminals TPG. DRAM core MCR receives a power supply voltage VCC through a power supply terminal PST.
Analog core ACR includes a phase locked loop circuit (PLL) generating an internal clock signal, an analog/digital converter converting an external analog signal to a digital signal, and a digital/analog converter converting a digital signal applied from large scale logic LG to an analog signal and outputting the analog signal.
DRAM core MCR which is a synchronous DRAM (SDRAM) captures data and an operation mode designation signal and outputs data in synchronization with an applied clock signal.
Large scale logic LG includes a memory control unit for carrying out processing such as image/audio information processing and controlling access to DRAM core MCR.
As shown in FIG. 26, provision of test interface circuit TIC makes it possible to completely disconnect DRAM core MCR from the logic portion (large scale logic LG) so as to directly access DRAM core MCR through test pin terminals TPG and to directly and externally control and observe DRAM core MCR. Such a test procedure is called direct memory access testing. By providing test interface circuit TIC, an operational test of a similar level to that for a general purpose DRAM (SDRAM) using a conventional memory tester can be performed.
FIG. 27 shows a configuration of test interface circuit TIC shown in FIG. 26 and associated portions.
Referring to FIG. 27, test pin terminals TPG include a pin terminal receiving a test clock signal TCLK1, a pin terminal receiving a test control signal TCMD for designating a test operation mode, a pin terminal receiving a test address TAD for designating a memory cell in DRAM core MCR which is to be accessed in a test mode, a pin terminal receiving write data TDin in the test mode, and a pin terminal receiving output data TDout from test interface circuit TIC in the test mode.
Test write data TDin applied to test interface circuit TIC and test output data TDout from test interface circuit TIC are set to the bit width of 8 bits, for example, similarly to a general purpose DRAM.
Test interface circuit TIC includes a latch/command decoder 1 capturing, in synchronization with test clock signal TCLK1, test control signal TCMD, test address TAD and test write data TDin applied to test pin terminals TPG, and performing processing such as decoding the test control signal to an internal command (operation mode designation signal) to be issued to DRAM core MCR and expanding test input data TDin of a 8-bit width to write data of 256 bits, a mode register 2 storing information such as the column latency of DRAM core MCR, a CA shifter 3 shifting, according to the column latency information stored in mode register 2, a read selection designation signal applied from latch/command decoder 1 to produce a read data selection signal RD_S, and a 256:8 selection circuit 4 selecting, according to read data selection signal RD_S from CA shifter 3, 8-bit data from the 256-bit read data read out from DRAM core MCR. Hereinafter, the 256:8 selection circuit is also referred to as a read data selection circuit.
As test peripheral circuits, a selector 5 selectively coupling DRAM core MCR and one of the large scale logic LG and test interface circuit TIC in response to test mode designation signal TE, a gate circuit 6 receiving clock signal CLK applied from the large scale logic LG, for example, in a normal operation mode and test clock signal TCLK1 applied in the test mode and supplying a clock signal DCLK to DRAM core MCR, and a gate circuit 7 transmitting to test interface circuit TIC 256-bit read data RD read out from DRAM core MCR at the time of activation of test mode designation signal TE are provided. 256-bit read data RD read out from DRAM core MCR is applied to the large scale logic LG without passing through selector 5. This is intended to apply read data at high speed to the large scale logic in the normal operation.
DRAM core MCR captures applied data and signals and outputs read data RD in synchronization with DRAM operational clock signal DCLK.
FIG. 28 shows in more detail the configuration of latch/command decoder 1 shown in FIG. 27.
Referring to FIG. 28, latch/command decoder 1 includes a latch circuit 1a responsive to a rise of test clock signal TCLK1 for capturing and latching test control signal TCMD, test address TAD and test write data TDin input to test pin terminals TPG, a command decoder 1b receiving and decoding test control signal TCMD and prescribed bits of test address TAD from latch circuit 1a and producing a command to designate an operation mode, a bit width expansion circuit 1c expanding 8-bit test write data TDin from latch circuit 1a to 256-bit test write data, and a latch circuit 1d responsive to a fall of test clock signal TCLK1 for capturing and latching output signals of command decoder 1b and bit width expansion circuit 1c. 
A test command TIFCMD, a test address TIFAD and test write data TIFDin are output from latch circuit 1d and applied to DRAM core MCR through selector 5. The command from command decoder 1b is also applied to mode register 2 and, when a mode register set mode is designated, directs mode register 2 to store address bits or test data.
As described above, latch circuit 1a assumes a latch state (or through state) in response to a rise of test clock signal TCLK1. Latch circuit 1d assumes a latch state (or through state) complementarily to latch circuit 1a in response to a fall of test clock signal TCLK1.
Command decoder 1b receives test control signal TCMD and prescribed address bits and generates internal commands for designating an operational mode, such as a mode register set command MRS, a no operation command NOP, a bank active command ACT, a bank precharge command PRE, a write command WRITE, a read command READ and an auto refresh command REFA.
FIG. 29 is a timing chart illustrating an operation of the test interface circuit shown in FIG. 27.
As shown in FIG. 27, DRAM core MCR transfers write data INDin and read data RD on different buses. For test pin terminals TPG as well, test input data TDin and test output data TDout during testing are transferred by using different pin terminals. Here, test directions for the DRAM core are received from an external memory tester.
First, a data reading operation from the DRAM core in the test mode will be described.
Referring to FIG. 29, in clock cycle #1, test mode control signal TCMD for generating read command (read operation designation signal) READ is input to direct DRAM core MCR to read data. In clock cycle #2, test control signal TCMD applied in clock cycle #1 is supplied, as internal control signal INCMD for designating read command READ, from test interface circuit TIC to DRAM core MCR through selector 5.
In the test mode, according to a test mode designation signal TE, selector 5 disconnects the large scale logic and DRAM core MCR, and selects a test interface command (test operation mode designation signal) TIFCMD, a test interface address TIFAD, test interface input data TIFDin output from test interface circuit TIC and transfers them to DRAM core MCR.
Gate circuit 7 transmits data RD read out from DRAM core MCR to test interface circuit TIC according to test mode designation signal TE. DRAM core MCR reads out internal data in synchronization with operation clock signal DCLK applied from gate circuit 6 and according to an internal address INADD applied at the same time. When column latency CL of DRAM core MCR is two clock cycles (hereinafter, such a case is also referred to as xe2x80x9cthe case of CL=2xe2x80x9d), valid read data is output at a rising edge of test clock signal TCLK1 in clock cycle #4 according to internal read command READ (INCMD) applied in clock cycle #2.
In test interface circuit TIC, CA shifter 3 shifts, according to test clock signal TCLK1, read data selection signal RD_S, which is made of the upper 5 bits of a column address included in test address TAD, for a clock cycle of column latency CL. When read data selection signal RD_S is generated from test address TAD, the delay time in test interface circuit TIC is included in addition to the shift period.
Therefore, at timing when 256-bit read data RD from DRAM core MCR reaches read data selection circuit 4 through gate circuit 7, that is, in clock cycle #4, read data selection signal RD_S from CA shifter 3 is also validated. Therefore, read data selection circuit 4 selects 8-bit data from 256-bit data according to read data selection signal RD_S ( less than 0 greater than ) and transmits the data as test output data TDout (D00) to a pin terminal group.
Then, a data writing operation for the DRAM core in the test mode will be described.
In clock cycle #2, test control signal TCMD indicating data writing is applied from an external memory tester to DRAM core MCR. Test control signal TCMD is decoded to write command (operation mode designation signal) WRITE indicating data writing by latch/command decoder 1. When the write command is applied, test write data TDin (DA) is also simultaneously applied to test pin terminals. Write command WRITE and test write data DA are also transferred in synchronization with test clock signal TCLK1 in test interface circuit TIC.
In latch/command decoder 1, for input data TDin, bit width expansion circuit 1c converts 8-bit test input data DA (TDin) to 256-bit internal write data DAin. In other words, an 8-bit data line is expanded to a 256-bit data line.
Furthermore, the external memory tester applies as test control signal TCMD a test control signal which is decoded to read command READ directing data reading in clock cycle #3, and a test control signal which is decoded to write command WRITE indicating data writing in the next clock cycle #4.
In this case, in clock cycle #5, internal write data DBin is applied to DRAM core MCR. Then, in clock cycle #6, 256-bit data Dout is read out from DRAM core MCR, and 8-bit read data D01 selected by read data selection circuit 4 according to read data selection signal RD_S ( less than 1 greater than ) is output as test data TDout from test pin terminals TPG.
Mode register 2 stores data indicating the number of cycles of column latency CL and signal propagation delay (one clock cycle in the example shown in FIG. 27) in test interface circuit TIC. CA shifter 3 carries out its shifting operation according to test clock signal TCLK1 for a period corresponding to the data stored in mode register 2, and thus data RD read out from DRAM core MCR can be selected at correct timing to output test data TDout.
By providing test interface circuit TIC as described above, it becomes possible to directly access DRAM core MCR from an external memory tester and to carry out direct memory access testing. Therefore, a necessary test for DRAM core MCR can be performed by using a memory tester for a general purpose SDRAM.
However, it is necessary to perform an operational test at an actual operating frequency of a DRAM core (hereinafter, such testing is also referred to as an AT-SPEED test) to ensure the operation of the DRAM core. Therefore, in view of higher frequency operation of a recent system LSI, an expensive high speed memory tester capable of supplying a high frequency test clock is necessary. That leads to a problem that the test cost of the DRAM core is increased.
An object of the present invention is to provide a configuration of a test interface circuit capable of performing an operational test for a memory core at an actual operating frequency even by using an inexpensive low speed memory tester in a semiconductor integrated circuit device equipped with the memory core.
In summary, the present invention is a semiconductor integrated circuit device including a memory circuit and a test interface circuit. The memory circuit operates in synchronization with an operational clock signal, and performs given operational directions. During testing, the test interface circuit supplies the operational clock signal and the operational directions to the memory circuit and communicates data with the memory circuit according to test directions input in synchronization with a test clock signal. The test interface circuit includes a frequency multiplication circuit multiplying the frequency of the test clock signal to generate an internal test clock signal to be supplied as the operational clock signal to the memory circuit.
According to another aspect of the present invention, a semiconductor integrated circuit device includes a memory circuit and a test interface circuit. The memory circuit operates in synchronization with an operational clock signal and performs given operational directions. During testing, the test interface circuit supplies the operational clock signal and the operation directions to the memory circuit and communicates data with the memory circuit according to test directions input in synchronization with a test clock signal. The test interface circuit includes a test clock control terminal receiving a selection signal for selecting a frequency of the operational clock signal during testing, and a frequency multiplication circuit generating, according to the test clock signal, an internal test clock signal to be supplied as the operational clock signal to the memory circuit, the frequency multiplication circuit outputting, according to the selection signal, one of the test clock signal and a clock signal generated by multiplying the frequency of the test clock signal as the internal test clock signal.
Therefore, a major advantage of the present invention is that, during testing, the test interface circuit capable of directly accessing the memory circuit according to the external test directions allows the memory circuit to be operated in synchronization with the internal test clock signal generated by multiplying the frequency of the test clock signal. It is therefore possible to carry out direct memory access testing at a high frequently for the memory circuit even by using a low speed memory tester.
Since executing/stopping of the frequency multiplication operation during internal test clock signal generation can be selected by inputting of the selection signal to the test clock control terminal, whether or not the frequency of the external test clock signal is multiplied can be selected in direct memory access testing for the memory circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.